Course Overview

This course explores the complete vertical stack of a computing system — from digital logic and number systems through the processor pipeline, assembly language, and operating system internals, concurrency, and file systems. Through a hands-on OS assignment, students build a minimal kernel in C and x86-32 NASM assembly, starting from a raw 512-byte MBR bootloader and culminating in a working RAM-disk file system running inside QEMU.

All lecture slides and notes align with Stallings, Computer Organization and Architecture, 10th edition. Every figure, section, and exercise cites the exact Stallings reference. Exam-style exercises with mark allocations appear throughout each lecture.

Lecture Slides & Notes

I

Hardware Fundamentals

Lectures 1–4 · Digital Systems & Computer Organisation

Computer System Fundamentals
Basic Elements · Registers · Instruction Cycle · Interrupts
Stallings Ch. 1–2 · Week 1
01
  • MAR, MBR, I/OAR, I/OBR register functions
  • Fetch-Execute cycle — 6-step register trace
  • 9-step interrupt sequence (save/restore)
  • Sequential vs. nested interrupt handling
  • I/O techniques: programmed, interrupt-driven, DMA
Memory Hierarchy & I/O Architecture
Hit Ratio · Cache Design · DMA · Multicore
Stallings Ch. 3–5 · Week 2
02
  • T_avg = T₁ + (1−H)×T₂ — hit ratio worked example
  • Direct, set-associative, fully-associative cache
  • DMA 7-step transfer protocol
  • MESI cache coherence protocol (4 states)
  • Intel Core i7 multicore organisation
Data Representation & Combinational Circuits
Number Systems · IEEE 754 · Boolean Algebra · Gates
Stallings App. A · Week 3
03
  • Sign-magnitude, 1's complement, 2's complement encoding
  • IEEE 754 single precision: sign / exponent / mantissa
  • Boolean algebra — De Morgan's laws, canonical forms
  • Half adder, full adder, ripple-carry adder
  • Multiplexer and decoder circuit design
Sequential Circuits & Computer Architectures
Flip-Flops · FSM · CISC vs RISC · Von Neumann vs Harvard
Stallings App. B · Week 4
04
  • D flip-flop and JK flip-flop timing diagrams
  • 7-step FSM design procedure (Moore and Mealy)
  • CISC vs. RISC — 10-attribute comparison table
  • Von Neumann vs. Harvard vs. Modified Harvard
  • Register file design with read/write ports
II

Processor Architecture & ISA

Lectures 5–7 · Performance, Pipelining & Assembly

Processor Architecture & ISA
ALU · Control Unit · MIPS Formats · Addressing · Performance
Stallings Ch. 12–13 · Week 5
05
  • Hardwired vs. microprogrammed control unit design
  • MIPS R-type, I-type, J-type instruction formats
  • 8 addressing modes with examples
  • T = N × CPI × T_clk — worked CPU performance
  • Amdahl's Law — speedup table for 20%/50%/80%
Pipelining, Branch Prediction & Parallelism
5-Stage Pipeline · Hazards · Flynn's Taxonomy · ILP
Stallings Ch. 14–17 · Week 6
06
  • IF → ID → EX → MEM → WB — pipeline timing diagram
  • Structural, RAW data, and control hazard resolution
  • 2-bit saturating counter branch predictor
  • Flynn's taxonomy: SISD / SIMD / MISD / MIMD
  • OOO execution, SMT, and VLIW approaches
Assembly Language & HW/SW Integration
x86-32 Registers · cdecl Convention · Stack Frames · Boot
Stallings Ch. 11 · Week 7
07
  • EAX/EBX/ECX/EDX/ESP/EBP/ESI/EDI roles
  • cdecl calling convention — 8-step stack protocol
  • Stack frame layout: args / ret-addr / saved-EBP / locals
  • CR0 bit 0 — Real Mode to Protected Mode transition
  • FAR JUMP and pipeline flush after CR0 write
III

Operating System Core

Lectures 8–9 · Processes, Scheduling & OS Assignment Stage 0–1

OS Overview & Process Models Stage 0
OS Objectives · Services · ISA/ABI/API · Evolution
Stallings Ch. 2–3 · Week 8
08
  • 3 OS objectives + "without it" implication column
  • 7 OS services with examples
  • ISA / ABI / API interface layers diagram
  • 4-era OS evolution (batch → time-sharing → personal → distributed)
  • 4 OS resource-management control tables
Process Description & Control Stage 1
PCB · Five-State Model · Context Switch · Scheduling
Stallings Ch. 3–9 · Week 9
09
  • PCB — 8 field groups with register-transfer detail
  • Five-state and seven-state process models
  • 7-step context switch (save/restore trace)
  • FCFS, SJF, SRTF, Round-Robin, Priority scheduling
  • Round-Robin Gantt chart — quantum = 2 ms worked example
IV

Concurrency, Memory & File Systems

Lectures 10–12 · OS Assignment Stages 2–4

Threads & Concurrency Control Stage 2
Threads · ULT vs KLT · Race Conditions · Mutual Exclusion
Stallings Ch. 4–5 · Week 10
10
  • ULT vs. KLT — 8-attribute comparison table
  • myglobal race condition — with and without mutex
  • 3 process interaction types and implications
  • Dijkstra's 6 requirements for mutual exclusion
  • CAS and XCHG spinlock implementations (x86)
Semaphores, Deadlocks & Memory Stage 3
semWait/Signal · Coffman Conditions · Banker's · Paging
Stallings Ch. 6–8 · Week 11
11
  • semWait and semSignal — full C implementation
  • 3-semaphore producer-consumer bounded buffer
  • 4 Coffman conditions for deadlock
  • Banker's Algorithm — safety sequence worked example
  • OPT, LRU, Clock page-replacement algorithms
File Systems, Protection & Review Stage 4
File Allocation · i-nodes · Protection Rings · Security
Stallings Ch. 11–12 · Week 12
12
  • Contiguous, FAT-linked, and i-node allocation methods
  • i-node multi-level indirection (single/double/triple)
  • x86 protection rings 0–3 and privilege transitions
  • 4 security goals: confidentiality, integrity, availability, accountability
  • 12-lecture summary table for exam revision

OS Assignment Articles

Assignment Overview

Build a Minimal OS in Five Stages

Over five stages you will build a complete minimal operating system in C and x86-32 NASM assembly, running inside QEMU. Each stage maps directly to OS lectures L08–L12. The extension ideas listed in each article are open-ended — well-tested, well-documented extensions earn bonus marks. Tag each stage as a release in your private GitLab repository.

Stage 0 — Boot & Shell Stage 1 — Scheduler Stage 2 — Threads & Mutex Stage 3 — Memory Manager Stage 4 — File System
Download Stage 0 Starter Student Guide
Booting Your OS: From Power-On to a Working Shell
MBR Bootloader · GDT · Protected Mode · VGA Driver · PS/2 Keyboard
Stage 0 · Corresponds to Lecture 07–08
0

A deep-dive into the x86 boot sequence. We write a 512-byte MBR in NASM, load the kernel via INT 0x13 extended read, set up a minimal three-entry GDT, transition the CPU from 16-bit Real Mode to 32-bit Protected Mode by setting CR0 bit 0, execute the mandatory FAR JUMP to flush the pipeline, and land in kernel_main(). We then build a text-mode VGA driver writing directly to 0xB8000 and a PS/2 keyboard driver for a working line-editing shell.

Extension Ideas for Students

  • Full ISO keyboard layout with Shift, CapsLock, and numeric keypad support in the scancode table
  • VGA scrolling buffer — circular ring, Page-Up / Page-Down support
  • ANSI escape-code colour support (ESC[31mESC[0m) in the VGA driver
  • Command history (up/down arrow) with a 20-entry ring buffer
  • Tab-completion scanning the command table for prefix matches
  • Replace the custom bootloader with a GRUB2 multiboot header and load as a standard ELF binary
Scheduling Processes: Building a Round-Robin Kernel
PCB Design · PIT 8253 · IRQ0 · Context Switch in NASM · ps Command
Stage 1 · Corresponds to Lecture 09
1

We design the pcb_t struct (state, stack pointer, entry point, PID), implement create_process(), program the i8253 PIT for 100 Hz clock interrupts on IRQ0, and write a PUSHAD/POPAD context-switch stub in NASM. The shell gains a ps command that displays all PCBs.

Extension Ideas for Students

  • Multi-level feedback queue (MLFQ) with 3 priority bands and ageing to prevent starvation
  • sleep(ms) syscall using the PIT tick counter and a wake-time-sorted sleep queue
  • fork(): duplicate the PCB, copy 4 KB stack, return 0 to child and child PID to parent
  • CFS-style virtual runtime (vruntime) with a sorted run-queue for proportional-share scheduling
Threads, Mutexes & Semaphores — Kernel Concurrency
Kernel Threads · mutex_t · semaphore_t · Race Condition · Producer-Consumer
Stage 2 · Corresponds to Lecture 10
2

We extend the kernel with lightweight kernel threads sharing a process's address space, implement a blocking mutex_t and a counting semaphore_t. The classic myglobal race condition demonstrates the problem — with and without a mutex. A bounded-buffer producer-consumer validates all three semaphores working together.

Extension Ideas for Students

  • Priority inheritance in the mutex: boost the lock holder's priority to the highest waiter's level
  • Read-write lock (rwlock_t): concurrent readers, exclusive writers with starvation prevention
  • Deadlock detector: periodically walk the resource-allocation graph with DFS looking for cycles
  • Implement the Readers-Writers problem with writer starvation prevention using a turn variable
Physical Memory Manager — Bitmap Allocator
BIOS E820 Map · Bitmap · pmm_alloc_frame · pmm_free_frame · meminfo
Stage 3 · Corresponds to Lecture 11
3

We parse the BIOS E820 memory map from the boot stage, build a bitmap (1 bit per 4 KB frame), and implement pmm_alloc_frame() and pmm_free_frame(). The shell gains a meminfo command showing total / used / free frame counts. Kernel identity-mapping ensures physical == virtual addresses throughout.

Extension Ideas for Students

  • Buddy allocator to reduce external fragmentation for multi-frame contiguous requests
  • Virtual memory manager: software-managed page table + #PF handler for demand paging
  • Slab allocator: kmalloc(n) / kfree(p) for variable-size kernel heap objects on top of the frame allocator
  • Clock-algorithm page replacement when physical frames are exhausted — swap to the RAM disk from Stage 4
RAM Disk File System — Inodes, Directories & VFS
Superblock · inode_t · Bitmap · POSIX API · ls / touch / cat / write
Stage 4 · Corresponds to Lecture 12
4

The final stage builds a POSIX-inspired file system on a 1 MB RAM disk. We implement a superblock, a bitmap for blocks and inodes, a flat directory structure, and a full open / read / write / close / unlink interface. Shell commands ls, touch, cat, and write validate the complete system.

Extension Ideas for Students

  • Single-indirect block pointer in the inode — expand max file size from 32 KB to 4 MB + 32 KB
  • Subdirectories: mkdir / cd / pwd with a per-process current-directory pointer stored in the PCB
  • Write-ahead journaling (8 KB log) so the FS survives a simulated crash and can replay on next mount
  • VFS abstraction layer: file_ops_t vtable shared by the RAM disk FS and a second ROM read-only FS

Additional Resources

📘

Textbook

Stallings, Computer Organization and Architecture, 10th Ed. All figures cited in every lecture.

🗂

Lecture Plan

12-week schedule with weekly objectives, Stallings chapters, and assignment milestones.

🚀

OS Starter Kit

Stage 0 source: Makefile, boot.asm, C kernel, VGA & keyboard drivers, QEMU run script.

🛠

Toolchain Setup

Ubuntu: apt install nasm gcc qemu-system-i386 make gdb. macOS: brew install nasm qemu.

🎯

Student Guide

Environment setup, Makefile targets, QEMU+GDB debugging workflow, and submission checklist.

💻

Submission

Private GitLab repo. Tag each stage: v0.1-stage0 through v0.5-stage4 for grading.

Learning Path

Part I Weeks 1–4 (L01–L04): Hardware Fundamentals — Computer organisation, memory hierarchy, DMA, number systems, Boolean algebra, combinational and sequential logic, FSM design, CISC vs. RISC, Von Neumann vs. Harvard.
Part II Weeks 5–7 (L05–L07): Processor Architecture & ISA — ALU and control unit design, MIPS formats, addressing modes, CPU performance equation, Amdahl's Law, five-stage pipeline, hazards, branch prediction, Flynn's taxonomy, x86-32 assembly, cdecl convention, and the complete boot sequence. OS assignment Stage 0 starts here.
Part III Weeks 8–9 (L08–L09): OS Core — OS objectives, services, ISA/ABI/API layers, four-era evolution, resource-management tables, PCB (8 field groups), five-state and seven-state process models, seven-step context switch, and five CPU scheduling algorithms. Connects to OS assignment Stage 1.
Part IV Weeks 10–12 (L10–L12): Concurrency, Memory & File Systems — Threads, race conditions, Dijkstra's 6 requirements, CAS/XCHG spinlocks, semaphores, producer-consumer, deadlocks, four Coffman conditions, Banker's Algorithm, page replacement, file allocation methods, i-node indirection, protection rings, and security goals. Connects to OS assignment Stages 2–4.

Course Structure

Part I: Hardware Fundamentals (L01–L04) — Computer organisation and registers, memory hierarchy and DMA, number systems and Boolean algebra, combinational and sequential logic, FSM design, and architecture taxonomy (CISC/RISC/Von Neumann/Harvard).

Part II: Processor Architecture & ISA (L05–L07) — ALU and control unit design, ISA formats and addressing modes, CPU performance, pipelining, hazards, branch prediction, Flynn's taxonomy, ILP, x86-32 NASM assembly, and the boot sequence.

Part III: OS Core (L08–L09) — OS objectives, services, and interface layers; process control blocks; five-state and seven-state process models; context switching; and CPU scheduling algorithms (FCFS, SJF, SRTF, Round-Robin, Priority).

Part IV: Concurrency, Memory & File Systems (L10–L12) — Threads, mutual exclusion, semaphores, deadlocks, Banker's Algorithm, page replacement, file allocation methods, i-node multi-level indirection, x86 protection rings, and OS security goals.